DETAILED PINOUT OF 555:

Internal equivalent diagram of 555:


Circuit diagram of 555:



Pin 1 (Ground):  The ground pin is the most-negative supply potential of the device, which is normally connected to circuit ground when operated from positive supply voltages.
Pin 2 (Trigger):  This pin is the input to the lower comparator and is used to set the latch, which in turn causes the output to go high. This is the beginning of the timing sequence in monostable operation. Triggering is accomplished by taking the pin from above to below a voltage level of 1/3 V+ (or, in general, one-half the voltage appearing at pin 5). The action of the trigger input is level-sensitive, allowing slow rate-of-change waveforms, as well as pulses, to be used as trigger sources. The trigger pulse must be of shorter duration than the time interval determined by the external R and C. If this pin is held low longer than that, the output will remain high until the trigger input is driven high again.
PRECAUTION:
If the trigger input remains lower than 1/3V+ for a time longer than the timing cycle, the timer will re trigger itself when termination of first output pulse.The voltage range that can be applied to this pin is between V+ and ground.
A dc current, termed the trigger current, must also flow from this terminal into the external circuit. This current is typically 500nA (nano-amp) and will define the upper limit of resistance allowable from pin 2 to ground. For an astable configuration operating at V+ = 5 volts, this resistance is 3 Mega-ohm; it can be greater for higher V+ levels.

Pin 3 (Output):  This is the output pin.Output can be taken with respect to ground or V+.

Pin 4 (Reset):  This pin is  used to reset the latch and return the output to a low state. The reset voltage threshold level is 0.7 volt, and a sink current of 0.1mA from this pin is required to reset the device. The reset input is an overriding function, that is, it will force the output to a low state regardless of the state of either of the other inputs. It may thus be used to terminate an output pulse prematurely, to gate oscillations from "on" to "off", etc. Delay time from reset to output is typically on the order of 0.5 µS, and the minimum reset pulse width is 0.5 µS. Neither of these figures is guaranteed, however, and may vary from one manufacturer to another. In short, the reset pin is used to reset the flip-flop that controls the state of output pin 3. The pin is activated when a voltage level anywhere between 0 and 0.4 volt is applied to the pin. The reset pin will force the output to go low no matter what state the other inputs to the flip-flop are in. When not used, it is recommended that the reset input be tied to V+ to avoid any possibility of false resetting.

Pin 5 (Control Voltage):  This pin allows direct access to the 2/3 V+ voltage-divider point, the reference level for the upper comparator. It also allows indirect access to the lower comparator, as there is a 2:1 divider  from this point to the lower-comparator reference input. By applying a voltage to this pin, it is possible to vary the timing of the device independently of the RC network. The control voltage may be varied from 45 to 90% of the Vcc in the monostable mode, making it possible to control the width of the output pulse independently of RC. When it is used in the astable mode, the control voltage can be varied from 1.7V to the full Vcc. Varying the voltage in the astable mode will produce a frequency modulated (FM) output. In the event the control-voltage pin is not used, it is recommended that it be bypassed, to ground, with a capacitor of about 0.01uF (10nF) for immunity to noise, since it is a comparator input. This fact is not obvious in many 555 circuits since I have seen many circuits with 'no-pin-5' connected to anything, but this is the proper procedure. The small ceramic cap may eliminate false triggering.
Pin 6 (Threshold):  Pin 6 is one input to the upper comparator (the other being pin 5) and is used to reset the latch, which causes the output to go low. Resetting via this terminal is accomplished by taking the terminal from below to above a voltage level of 2/3 V+ (the normal voltage on pin 5). The action of the threshold pin is level sensitive, allowing slow rate-of-change waveforms. The voltage range that can safely be applied to the threshold pin is between V+ and ground. A dc current, termed the threshold current, must also flow into this terminal from the external circuit. This current is typically 0.1µA, and will define the upper limit of total resistance allowable from pin 6 to V+. For either timing configuration operating at V+ = 5 volts, this resistance is 16 Mega-ohm. For 15 volt operation, the maximum value of resistance is 20 MegaOhms.
Pin 7 (Discharge):  This pin is connected to the open collector of a npn transistor (Q14), the emitter of which goes to ground, so that when the transistor is turned "on", pin 7 is effectively shorted to ground. Usually the timing capacitor is connected between pin 7 and ground and is discharged when the transistor turns "on". The conduction state of this transistor is identical in timing to that of the output stage. It is "on" (low resistance to ground) when the output is low and "off" (high resistance to ground) when the output is high. In both the monostable and astable time modes, this transistor switch is used to clamp the appropriate nodes of the timing network to ground. Saturation voltage is typically below 100mV (milli-Volt) for currents of 5 mA or less, and off-state leakage is about 20nA (these parameters are not specified by all manufacturers, however).

Pin 8 (V +):  The V+ pin (also referred to as Vcc) is the positive supply voltage terminal of the 555 timer IC. Supply-voltage operating range for the 555 is +4.5 volts (minimum) to +16 volts (maximum), and it is specified for operation between +5 volts and +15 volts. Sensitivity of time interval to supply voltage change is low, typically 0.1% per volt. There are special and military devices available that operate at voltages as high as 18 volts.


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